1. Field of the Invention
This invention relates to a silicon wafer and a method of producing the same, and more particularly to a silicon wafer having a gettering means suitable for semiconductor device in very thin package and a method of producing the same.
2. Description of the Related Art
Recently, since some chips are set into the same package, for example, as in a multi-chip package (MCP) with higher integration of the semiconductor device, or as a matter of convenience in the packaging, it becomes widened to use a very thin silicon wafer. In advanced products will be used a silicon wafer having a thickness of 15 to 20 μm.
In general, when a silicon wafer is applied to a semiconductor process, there is a problem that a heavy metal as an impurity may be incorporated into the silicon wafer. The incorporation of the heavy metal significantly produces a bad influence on the device characteristics, e.g. bad pause time, bad retention, bad junction leakage and dielectric breakdown of oxide film. Therefore, it is common to adopt a gettering method for suppressing the diffusion of heavy metal into a device-forming (active) region located at a front face side of the silicon wafer.
However, the silicon wafer being thin in the thickness forms substantially an active layer, so that it hardly has a gettering site (capture region) on metal contamination anticipated in a packaging step. That is, it is required to form an active region for device formation in a front surface layer of the silicon wafer, and hence it is required to form a region having no defect due to oxygen precipitates (denuded zone: DZ layer) through a heat treatment. At the same time, an oxygen precipitate layer is formed inside the wafer by the heat treatment, which serves as a gettering site. Therefore, as the silicon wafer is thinned, the most part thereof is constituted with non-defective region.
As an example of forming the gettering site by the heat treatment,
JP-A-2000-269221 discloses that two-stage heat treatment and subsequent mirror polishing are conducted. However, the gettering site is in a depth region of 90 μm from the surface as described in the paragraph [0018] of JP-A-2000-269221, which is not applicable for the above thinning of the silicon wafer.